High speed digital signal processor architecture

Details High speed digital signal processor architecture High speed digital signal processor architecture

1983-06-01

1986-03-04

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 700, G06F 906

Patent

active

045743487

ABSTRACT:
A data processor uses complex instructions and a sequence controller to cause first and second fields of such instructions to process data, respectively, by first and second ALUs, with a third field of such instructions containing address information for addressing locations in a data addressing unit, generating addresses for selecting such data from a data memory storage device.

REFERENCES:
patent: 3445822 (1969-05-01), Driscoll
patent: 3614742 (1971-10-01), Watson et al.
patent: 3657736 (1972-04-01), Boom et al.
patent: 3671942 (1972-06-01), Knollman et al.
patent: 3710351 (1973-01-01), Nakamura
patent: 3720920 (1973-03-01), Watson et al.
patent: 3774157 (1973-11-01), Tsui
patent: 3787673 (1974-01-01), Watson et al.
patent: 3943494 (1976-03-01), Holmes, Jr. et al.
patent: 4071890 (1978-01-01), Pandeya
patent: 4075704 (1978-02-01), O'Leary
patent: 4096571 (1978-06-01), Vander Mey
patent: 4096572 (1978-06-01), Namimoto
patent: 4128881 (1978-12-01), Yamamoto et al.
patent: 4153934 (1979-05-01), Sato
patent: 4171536 (1979-10-01), Heuer et al.
patent: 4323981 (1982-04-01), Nakamura
patent: 4435765 (1984-03-01), Uchida et al.
patent: 4449184 (1984-03-01), Pohlman, III et al.

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