Method of making a saturation-limited bipolar transistor device

Details Method of making a saturation-limited bipolar transistor device Method of making a saturation-limited bipolar transistor device

1983-02-22

1984-05-08

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 148 15, 148187, 148188, H01L 21225

Patent

active

044466110

ABSTRACT:
A saturation-limited bipolar transistor device or circuit and a method of making same are provided which includes a merged NPN transistor and a PNP transistor structure formed so as to produce denser cells or circuits. A simple process is used to form the structure which includes a double diffused technique for making the PNP transistor. The PNP transistor has a double diffused emitter-base arrangement wherein the emitter is asymmetrically positioned with respect to the base so as to also serve as a contact for the base of the NPN transistor. The PNP transistor limits the input current by bypassing excess current to a silicon semiconductor substrate or chip. The structure includes an N type epitaxial layer formed on an N type subcollector with a P type region provided near the surface of the epitaxial layer. The epitaxial layer serves as the NPN collector and as the PNP base contact region. A first N type region is formed through the P type region extending from the surface of the epitaxial layer to the subcollector dividing the P type region into first and second sections which serve as the PNP collector region and the NPN base region, respectively. A second N type region is formed in the second section of the P type region at the surface of the epitaxial layer acting as the NPN emitter and a P+ region is formed in the first N type region at the surface of the epitaxial layer extending into the second section of the P type region which forms the NPN transistor base. This P+ region serves as the PNP emitter and as the NPN base contact.

REFERENCES:
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patent: 3821776 (1974-06-01), Hayashi et al.
patent: 4021687 (1977-05-01), Yoshimura
patent: 4058419 (1977-11-01), Tokamaru et al.
patent: 4064526 (1977-12-01), Tokumaru et al.
patent: 4069428 (1978-01-01), Reedy
patent: 4110126 (1978-08-01), Bergeron et al.
patent: 4190466 (1980-02-01), Bhattacharyya et al.
IBM Technical Disclosure Bulletin, vol. 22 No. 2, Jul. 1979, by R. Remshardt et al. on pp. 617-618 "Active Injection Memory Cell".

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