Semiconductor memory device with improved address wiring arrange

Details Semiconductor memory device with improved address wiring arrange Semiconductor memory device with improved address wiring arrange

1989-02-28

1990-08-28

Fears, Terrell W.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, G11C 1300

Patent

active

049531344

ABSTRACT:
A semiconductor memory device having improved address wiring and address decoding structures is disclosed. The memory device comprises a plurality of address decoders arranged separately, an address buffer for generating "n"-bits of address signals, a set of address wirings coupled to said address buffer and the address decoders, the number of address wirings being "n", and a plurality of inverting circuits provided for the address decoders, each of inverting circuits coupled to the address wirings and being responsive to the signals at the address wirings for generating their complementary signals to be applied to the associated address decoder.

REFERENCES:
patent: 4727516 (1988-02-01), Yoshida et al.

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