Circuitry for and method of controlling an instruction buffer in

Details Circuitry for and method of controlling an instruction buffer in Circuitry for and method of controlling an instruction buffer in

1988-04-05

1990-08-28

Heckler, THomas M.

Boots, shoes, and leggings

3649381, 3649393, 3649428, 3649472, 36496422, 36496426, G06F 1208

Patent

active

049531212

ABSTRACT:
A method of controlling instructions in a data-processing system, wherein instructions including branching instructions pointing to an instruction address defining a branch address are loaded in sequence in response to a loading indicator that is always increased by no more than a prescribed difference in relation to an instruction address (BRA) that is constantly to be increased in accordance with one program runthrough and ahead of the instructions address, from instruction addresses in a main memory (MEM) into an instruction buffer memory (IBUF) and addressable therein by an instruction address. Instructions are supplied from the instruction buffer memory to an instruction decoder (IDEC) for exection, by comparing the branch address of a branching instruction while a program is being run with an instruction address range of instructions in the instruction buffer memory and, if the branch address is in said instruction address range, directly calling that addressed instruction out of the instruction buffer memory and, if the branch address is outside said instruction range, the branch address is accepted as a new loading indicator and the old instruction range is erased. The loading indicators (AP, FA) are supplied to the main memory (MEM) and at least selected bits of the loading indicator that are necessary for addressing the instruction buffer memory (IBUF) are supplied to an address pipeline (APL).

REFERENCES:
patent: 4467414 (1984-08-01), Akagi et al.
patent: 4521850 (1985-06-01), Wilhite et al.
patent: 4646233 (1987-02-01), Weatherford et al.
patent: 4714994 (1987-12-01), Oklobdzija et al.
Van Loo, "Maximaze Performance by Choosing Best Memory", Computer Design, Aug. 1, 1987, pp. 89-94.
Computer Design 21, Apr. 1982, pp. 63-64.

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