Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1983-02-17
1984-10-23
Hearn, Brian E.
Metal working
Method of mechanical manufacture
Assembling or joining
29578, 148174, 357 22, H01L 2946, H01L 2976
Patent
active
044779631
ABSTRACT:
Semiconductor electrode structure with low parasitic capacitance and method for forming low capacitance first and second electrodes in a semiconductor device, such as a static induction transistor, while avoiding the requirement for precision mask alignment and mask to mask registration. During formation of electrode contacts, the first electrodes are protected by silicon nitride and a low resistivity silicon layer is grown over the semiconductor wafer, forming epitaxial regions over the second electrodes of a polycrystalline region over protected portions of the wafer. The silicon layer is selectively etched by a mixture which removes the polycrystalline region but does not appreciably affect the epitaxial regions. Second electrode metallic contacts are made in enlarged regions of the second electrodes where mask alignment is not critical. The reduction in contact window overlap by metallic contacts reduces parasitic capacitance.
REFERENCES:
patent: 3936331 (1976-02-01), Luce et al.
patent: 4141023 (1979-02-01), Yamada
patent: 4151019 (1979-04-01), Tokumaru et al.
patent: 4175317 (1979-11-01), Aoki et al.
patent: 4352238 (1982-10-01), Shimbo
Auyang Hunter L.
GTE Laboratories Incorporated
Hearn Brian E.
Yeo J. Stephen
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