Patent
1985-05-02
1987-09-29
Carroll, J.
357 234, 357 55, H01L 2978, H01L 2702, H01L 2906
Patent
active
046972013
ABSTRACT:
In a power MOS FET, a channel forming region is established to be in contact, through a semiconductor oxide layer, with that portion of a gate region which is located on a groove extending through a source region into a drain region and with that portion of the gate region layer which is located on a planar portion where no such groove is formed. With such construction, the "on" resistance of the FET can be decreased without increasing the size thereof.
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Carroll J.
Nissan Motor Company Limited
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