Patent
1991-02-01
1992-04-21
James, Andrew J.
357 52, H01L 2972, H01L 2934
Patent
active
051073200
ABSTRACT:
A method and apparatus for reducing interconnection capacitance. A lightly doped buried layer is provided in or on a substrate below a field oxide region. The capacitance of an interconnect on the field oxide is significantly reduced by the lightly doped buried layer. When using a p-type substrate, the lightly doped buried layer may, for example, be a lightly doped (10.sup.13 /cm.sup.3) n-type region. Junction capacitance of, for example, a bipolar transistor is also reduced.
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Copy of U.S. application Ser. No. 079,626, filed Jul. 29, 1987.
James Andrew J.
Meier Stephen D.
National Semiconductor Corporation
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