Programmable memory circuit

Details Programmable memory circuit Programmable memory circuit

1985-10-16

1987-09-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307449, 307452, 307518, 328119, 365189, 365226, G11C 800, H03K 19094, H03K 522, G01R 19145

Patent

active

046971068

ABSTRACT:
A programmable memory circuit adapted to access a memory comprises a decoder responsive to address input signals, an access line, a transfer gate connected between the decoder and the access line, and a selective voltage supply circuit connected to the access line. The transfer gate is responsive to a read/write switch signal to connect the decoder to the access line in the read mode and disconnect the decoder from the access line in the write mode. The selective voltage supply circuit is also responsive to the read/write switch signal to provide on the access line different voltage levels in accordance with read/write mode. The access line assumes, in the read mode, one voltage level which is equal to the level of the output signal from the decoder and in the write mode the other voltage level.

REFERENCES:
patent: 3594736 (1968-11-01), Hoffman
patent: 4094012 (1978-06-01), Perlegos et al.
patent: 4583205 (1986-04-01), Watanabe
IBM Tech. Disc. Bul., vol. 19, No. 5, Oct. 1976, p. 1681, Enhancement/Depletion Decoder Circuit.

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