Programmable gate array and methods for its fabrication

Details Programmable gate array and methods for its fabrication Programmable gate array and methods for its fabrication

1990-10-09

1992-04-21

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 52, 437170, 437 43, 437922, H01L 7170, H01L 2700

Patent

active

051067730

ABSTRACT:
Circuitry 12 is formed at the face of a layer semiconductor 34. The circuitry includes a plurality of contact points 22 and 24. At least one anti-fuse 14 is formed in a layer vertically displaced from circuitry 12. Anti-fuse 14 is operable to selectively connect together certain ones of said contact points 22 and 24.

REFERENCES:
patent: 4569120 (1986-02-01), Stacy et al.
patent: 4823181 (1989-04-01), Mohsen et al.
patent: 4876220 (1989-10-01), Mohsen et al.
patent: 4914055 (1990-04-01), Gordon et al.
patent: 4916090 (1990-04-01), Motai et al.
patent: 4943538 (1990-07-01), Mohsen et al.
William S. Carter, et al., article entitled "A User Programmable Reconfigurable Logic Array", 1986, Custom Integrated Circuits Conference, 1986 IEEE.
Sau Wong et al., article entitled "CMOS Erasable Programamble Logic with Zero Standby Power", 1986 IEEE International Solid-State Circuits Conference.
Abbas El Gamal, et al., article entitled "An Architecture for Electrically Configurable Gate Arrays", IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989.

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