Fishing – trapping – and vermin destroying
Patent
1990-03-29
1992-04-21
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 44, 437162, 437 2, 148DIG9, H01L 21328
Patent
active
051067650
ABSTRACT:
A process for producing a semiconductor device provided with a bipolar transistor and a gate-insulated transistor in which a bipolar semiconductor domain is formed on a semiconductor layer of a first conductivity type. An oxide layer is formed on the bipolar semiconductor domain and on the remaining semiconductor layer. The oxide layer is selectively removed to form an aperture in an area at least on the semiconductor domain, and an emitter domain is formed on the bipolar semiconductor domain. Plural polysilicon layers, each having an impurity of the first conductivity type, are formed on the aperture and on the oxide layer as a gate electrode of the gate-insulated transistor. The impurity of the first conductivity type from the polysilicon layers on the aperture is diffused by thermal oxidation into the bipolar semiconductor domain to form an emitter domain of the first conductivity type, and to form and develop thermal oxide layers at least on the upper and lateral faces of the polysillicon layers constituting the gate electrode. Ions of an impurity of the opposite conductivity type are implanted to form source and drain domains of the gate-insulated transistor by a thermal treatment, utilizing the polysilicon layers constituting the gate electrode and the thermal oxide layers as masks. A photosensor is formed in the semiconductor substrate having at least a photoreceiving element being separated from other semiconductor elements by an isolation region separating domain composed of a semiconductor of the first conductivity type.
REFERENCES:
patent: 4034395 (1977-07-01), Abdelrahman
patent: 4445268 (1984-05-01), Mamma et al.
patent: 4475279 (1984-10-01), Gahle
patent: 4484388 (1984-11-01), Iwasaki
patent: 4486942 (1984-12-01), Hirao
patent: 4536945 (1985-08-01), Gray et al.
patent: 4637125 (1987-01-01), Iwasaki et al.
patent: 4651016 (1987-03-01), Hirao
patent: 4665422 (1987-05-01), Hirao et al.
Kondo Shigeki
Mizutani Hidemasa
Canon Kabushiki Kaisha
Hearn Brian E.
Quach T. N.
LandOfFree
Process for making a BiMOS does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for making a BiMOS, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for making a BiMOS will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1585656