Poly-sidewall contact semiconductor device method

Details Poly-sidewall contact semiconductor device method Poly-sidewall contact semiconductor device method

1985-10-08

1987-09-29

Hearn, Brian E.

Fishing, trapping, and vermin destroying

148DIG50, 148DIG164, 148DIG11, 156653, 357 59, 357 34, 357 49, 437228, H01L 21283, H01L 21302

Patent

active

046960970

ABSTRACT:
Improved semiconductor devices having minimum parasitic junction area are formed by using multiple buried polycrystalline conductor layers to make lateral contact to one or more pillar-shaped epitaxial single crystal device regions. The lateral poly contacts are isolated from each other and from the substrate and have at least one polycrystalline pillar extending to upper surface of the device to permit external connections to the lower poly layer.
The structure is made by depositing three dielectric layers with two poly layers sandwiched in between. Holes are anisotropically etched to the lowest poly layer and the substrate. A conformal oxide is applied over the whole structure and anisotropically etched to remove the bottom portions in the hole where the poly pillar and the isolation wall are to be formed and isotropically where the single crystal pillar is to be formed. The remaining oxide regions isolate the buried conductor layers, contacts, and isolation walls. The polycrystalline pillar extending from the lowest poly layer to the device surface is formed at the same time as the epi-pillar. The structure may be made self-aligned and self-registering.

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