Process for isolation using self-aligned diffusion process

Fishing – trapping – and vermin destroying

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156653, 156657, 437 89, 437913, 437962, 437981, H01L 2131

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046960953

ABSTRACT:
A process is disclosed for improving the isolation between semi-oxide insulated devices, formed on mesa structures. In the fabrication of such devices, a silicon substrate is provided. Patterned regions of one type of conductivity are formed in a major surface of the substrate and an epitaxial layer of silicon is formed on the substrate over the major surface. A patterned mask layer is formed on the epitaxial layer and is etched to expose portions of the epitaxial layer. The exposed portions of the epitaxial layer are removed to form the mesa structures, which overlie the doped patterned regions. Regions of opposite conductivity, called channel stops, are then formed in the substrate between the patterned regions. After filling in the areas between the mesa structures with a field oxide, the devices (bipolar or MOS transistors) are formed on the mesa structures.
The process of the invention utilizes as a mask structure a mask having a combination of properties (composition and thickness) related to the subequent processing. The mask permits use of an anisotropic etchant to define the mesa structures and to undercut the mask. An oxide layer is formed on the side walls of the mesa structures and on those portions of the substrate exposed during the mesa-defining step. Those portions of the oxide layer underlying openings in the mask structure are removed to expose portions of the substrate, which encompass regions between the doped patterned regions. The channel stop dopant is introduced into the regions between the patterned regions.

REFERENCES:
Benjamin, IBM Technical Disclosure Bulletin, vol. 22, No. 7, Dec. 1979, "Self-Aligned Recessed Oxide . . . Formation", pp. 2749-2750.

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