Paged memory management unit which evaluates access permissions

Details Paged memory management unit which evaluates access permissions Paged memory management unit which evaluates access permissions

1988-07-21

1989-12-26

Shaw, Gareth D.

Boots, shoes, and leggings

3642563, 3642564, 36424341, 3642543, 3642466, G06F 1210, G06F 1214

Patent

active

048902233

ABSTRACT:
A paged memory management unit (PMMU) adapted to translate each of a plurality of logical addresses into a corresponding physical address using a selected one of a plurality of descriptors comprising one or more translation tables stored in a memory, the PMMU assembling each of the logical addresses and the corresponding physical address into a respective translator. In general, the PMMU includes: a cache having a plurality of storage locations for storing the translators, each of the storage locations including a write protect indicator and a read protect indicator adapted to be selectively set; translation control logic for storing an assembled translator in a selected one of the storage locations, the translation control logic setting the write protect indicator of the one storage location in response to a write protect signal associated with the descriptor used to assemble the translator and the read protect indicator of the one storage location in response to a read protect signal associated with that descriptor; and access control logic for preventing the translator from being used to translate the logical address in support of a write operation if the write protect indicator of the one storage location is set or in support of a read operation if the read protect indicator of the one storage location is set. In the preferred form, the logical address has an access privilege level associated therewith and the descriptor includes a selected write access privilege level and a selected read access privilege level, the translation control logic setting the write protect indicator of the one storage location if the access privilege level associated with the logical address is logically less than the write access privilege level and the read protect indicator of the one storage location if the access privilege level associated with the logical address is logically less than the read access privilege level.

REFERENCES:
patent: 4392201 (1983-07-01), Brown et al.
patent: 4442484 (1984-04-01), Childs, Jr. et al.
patent: 4525780 (1985-06-01), Bratt et al.
patent: 4669043 (1987-05-01), Kaplinsky
patent: 4763244 (1988-08-01), Moyer et al.
patent: 4763250 (1988-08-01), Keshlear et al.
MCG8851 Paged Memory Management Unit User's Manual, 1986 by Motorola Inc., pp. 5-1 to 5-30 and 7-1 to 7-16.
MCG8020 32-Bit Microprocessor User's Manual, 1984 by Motorola Inc., pp. 8-6.

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