Signed digit adder circuit

Details Signed digit adder circuit Signed digit adder circuit

1988-03-31

1989-12-26

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 750

Patent

active

048901270

ABSTRACT:
A signed digit adder (10) includes a plurality of cells (12) which input signals X.sub.s, X.sub.m, Y.sub.s, Y.sub.m, R.sub.-1 and U.sub.-1, where X.sub.s and X.sub.m are the sign and magnitude bits of one digit of a signed bit representation. Similarly, Y.sub.s and Y.sub.m are the sign and magnitude bits of the second operand. R.sub.-1 and U.sub.-1 are signals received from the preceding cell (12). Each cell outputs R and U bits, and the sum bits Z.sub.s and Z.sub.m. Each cell (12) comprises function blocks (14-26) which determine the outputs from the given inputs. Function block (14) determines the output R as NOT(X.sub.s +Y.sub.s). Function block (20) determines the output U=E.multidot.NOT(R.sub.-1)+NOT(E).multidot.NOT(Q) where Q=(NOT (X.sub.s)+NOT (Y.sub.s)).multidot.X.sub.m. The determination of Q is performed in function block (16). Function block (24) determines the output Z.sub.s =U.sub.-1 .multidot.T and function block (26) determines the output Z.sub.m =U.sub.-1 XOR (NOT (T)). T is determined in function block (22)=E XOR (NOT (R.sub.-1)). E is determined in function block (18) as X.sub.m XOR Y.sub.m. Function blocks (14-26) are optimized for speed relative to the temporal validity of the inputs.

REFERENCES:
patent: 3462589 (1969-08-01), Robertson
Arizienis, "Binary-Compatible Signed-Digit Arithmetic", Pro.-Fall Joint Computer Conference, 1964, pp. 663-672.
Metropolis et al, "Significant Digit Computer Arithmetic", IRE Trans. on Electronic Computers, Dec. 1958, pp. 265-267.
Avizienis, "Signed-Digit Number Representations for Fast Parallel Arithmetic", IRE Trans. on Electronic Computers, Sep. 1961, pp. 389-400.
Atkins, "Design of the Arithmetic Units of ILLIAC III: Use of Redundancy and Higher Radix Methods", IEEE Trans. on Computers, C-19, No. 8, 8/1970, pp. 720-733.
Harata et al, "High Speed Multiplier Using a Redundant Binary Adder Tree" in Proc. IEEE ICCD '84, Oct. 1984, pp. 165-170.
Takagi et al, "High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree", IEEE Trans. on Computers, vol. C-34, No. 9, Sep. 1985, pp. 789-796.

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