Semiconductor integrated circuit having stacked integrated injec

Details Semiconductor integrated circuit having stacked integrated injec Semiconductor integrated circuit having stacked integrated injec

1981-04-03

1984-07-10

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307477, H03K 19091, H03K 19092

Patent

active

044594968

ABSTRACT:
In a stacked, multilayer IIL (integrated injection logic) circuit, with which power consumption can be significantly reduced, a discharging circuit constructed of an IIL constant-current circuit or of a resistor is provided for one of transistors which are used for shifting the level of a signal from an IIL circuit of a top layer to an IIL circuit of a bottom layer, so that signal transmission therebetween is prevented from deterioration. A charging circuit may be added to another transistor, while a diode may be interposed between these transistors. Additional diodes may be interposed between adjacent layers for speeding up the signal transmission from one layer to another upper layer.

REFERENCES:
patent: 4009397 (1977-02-01), Mulder et al.
patent: 4013901 (1977-03-01), Williams
patent: 4109162 (1978-08-01), Heuser et al.
patent: 4243896 (1981-01-01), Chapron
patent: 4256984 (1981-03-01), Kojima
Kaneko et al., "Stacked I.sup.2 L Circuit", IEEE Journal of Solid-State Circuits, Apr., 1977, pp. 210-212.

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