Fishing – trapping – and vermin destroying
Patent
1987-12-23
1989-12-26
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 90, 437924, 437974, 437984, 156662, 357 68, H01L 2122
Patent
active
048898325
ABSTRACT:
A process for forming backside contacts includes first forming an etch stop layer (12) beneath the surface of a silicon substrate. An active circuit is then formed in the silicon surface and associated metal interconnecting layers formed on the upper surface of the substrate. A planarizing layer is then formed on the upper surface of the substrate which is operable to be connected to a mechanical support. Thereafter, the backside of the substrate is etched away up to the etch stop layer (12). The thickness of the remaining substrate between the metal layers on the upper surface and the etch stop layer is sufficiently thin that the alignment marks on the upper surface can be seen through the substrate. These alignment marks are utilized to form vias from the backside to the active elements and then deposit and pattern interconnecting layers on the backside.
REFERENCES:
patent: 3133336 (1959-12-01), Marinace
patent: 3433686 (1966-01-01), Marinace
patent: 3493820 (1970-02-01), Rosvold
patent: 3787252 (1974-01-01), Filippazzi et al.
patent: 3944447 (1976-03-01), Magdo et al.
patent: 4169000 (1979-09-01), Riseman
patent: 4784970 (1988-11-01), Solomon
Anderson Rodney M.
Hearn Brian E.
Pawlikowski Beverly A.
Sharp Melvin
Sorensen Douglas A.
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