Fishing – trapping – and vermin destroying
Patent
1988-08-16
1989-12-26
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 67, 437 72, 148DIG105, 156643, 156664, H01L 2176
Patent
active
048898287
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
The present invention relates to a process for the production of electrical isolation zones in a CMOS integrated circuit.
It more particularly applies to the microelectronics field whenever it is necessary to electrically isolate from one another the n and p components of a circuit (transistors, diodes, etc.) produced on a monocrystalline silicon substrate. The invention can be more particularly used for the production of logic gates, flip-flops, random access or read-only memories, etc.
The search for a high integration density in CMOS integrated circuits requires the use of a special isolation technique between the different components of said circuits and specifically between their n channel transistors and their p channel transistors.
One of the recent isolation techniques used for this purpose is based on producing an isolating trench in the semiconductor substrate, said trench being oxidized and then filled with a material, such as polycrystalline silicon or silicon dioxide. Filling takes place by the deposition of the filling material over the entire surface of the integrated circuit, followed by the removal of the excess of said material deposited outside the trenches. Above the said trench is produced a local field oxide (LOCOS).
This technique of isolation by trench surmounted by a local field oxide has more particularly been described in an IEDM article in 1982, pp 237 to 240 and entitled "Deep Trench Isolated CMOS Devices".
This isolation technique makes it possible to achieve considerable isolation depths (several micrometres) between the different integrated circuit components, whilst ensuring a good surface isolation and whilst preventing the short-circuiting of the n channel transistors and the p channel transistors, said phenomenon being known as latch up.
Unfortunately, in such an isolation technique, the problem arises of an inversion of the electrical conductivity on the sides of the isolation trenches and therefore of the formation of parasitic channels, when the end of the channels of the transistors touch the trenches, where the transistor gates pass on to the latter. This problem of parasitic channels is more particularly described in an IEDM article in 1983, pp 23 to 26 and entitled "Characterization and Modelling of the Trench Surface Inversion Problem for the Trench Isolated CMOS Technology" by Kit M. CHAM et al. It makes it necessary to move the transistors away from the isolation trenches and more particularly the n channel transistors of said circuits, by producing a field oxide region between the trenches and the transistors at the place where the gate of said transistors passes onto the corresponding lateral isolation thereof, thus limiting the integration density of the said circuits.
Moreover, the positioning of isolation trenches between the n regions and the p regions of the substrate in which will be respectively produced the p channel transistors and the n channel transistors of the integrated circuit requires the use of several lithography masks, one mask for defining the location of the n regions and another mask for defining the location of the p regions, which are difficult to reciprocally position and which bring about a further limitation to the integration density of the CMOS circuits.
The present invention relates to a process for the production of electrical isolation zones in an integrated CMOS circuit making it possible to obviate the various disadvantages referred to hereinbefore.
In particular, the integrated circuit obtained according to the invention and using the procedure of isolating by isolation trenches, has a much higher integration density than that of the prior art CMOS circuits. Moreover, said circuit has no electrical conductivity inversion on the sides of the trenches and therefore no parasitic channels.
More specifically, the present invention relates to a process for the production of electrical isolation zones serving to isolate the n regions from the p regions of a CMOS integrated circuit formed in a silicon substrate, charact
REFERENCES:
patent: 4546538 (1985-10-01), Suzuki
patent: 4595452 (1986-06-01), Landau et al.
patent: 4676869 (1987-06-01), Lee et al.
Miller et al., Solid State Technology (Dec. 1982), pp. 85-90.
Rung et al., IEDM (1982), pp. 237-240.
Kudoh et al., J. Electrochem. Soc.: Solid State Science and Technololgy (Aug. 1986), pp. 1666-1670.
Cham et al., IEDM (1983), pp. 23-26.
Patent Abstracts of Japan, vol. 10, No. 104 (E-397), 19-Apr.-1986, p. 2161 & JP, A, 60244037, 60244043 (Toshiba K.K.) 3--Dec.-1985.
Chaudhuri Olik
Commissiriat A l'Energie Atomique
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