Memory testing device

Details Memory testing device Memory testing device

1988-12-21

1990-09-18

Smith, Jerry

Excavating

371 251, 371 27, G06F 1100

Patent

active

049583450

ABSTRACT:
In a memory testing device for testing a memory capable of effecting a write and a read in pixel, plane and block modes, there are provided a pattern generator for generating an address and data for supply to the memory under test and a buffer memory which has memory chips equal in number to the square of the number of bits of the data. The same data as that to be written in the memory under test is written in the buffer memory in the same mode as in the memory under test, and the data is read out in the same mode as in the memory under test. The data thus read out of the buffer memory is used as expected value data for logical comparison with data read out of the memory under test.

REFERENCES:
patent: 4369511 (1983-01-01), Kimura
patent: 4370746 (1983-01-01), Jones
patent: 4742474 (1988-05-01), Knierim
patent: 4775857 (1988-10-01), Staggs
patent: 4788684 (1988-11-01), Kawaguchi
patent: 4807229 (1989-02-01), Tada
patent: 4835774 (1989-05-01), Ooshima

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