Methodology for making logic circuits

Details Methodology for making logic circuits Methodology for making logic circuits

1983-11-21

1986-05-27

Gruber, Felix D.

Boots, shoes, and leggings

307469, 364490, 364716, H03K 19094

Patent

active

045919933

ABSTRACT:
A methodology is provided for reducing an arbitrary Boolean logic expression to static CMOS circuits by the use of a general matrix of P channel devices and N channel devices which are interconnected in accordance with the terms of Boolean logic expressions derived from a truth table. More specifically, from a Boolean expression a sum-of-products expression giving the 1 binary data outputs of a truth table having a 0 input is found. This is accomplished by complementing, or barring, the literals which are a binary 1 when the output is 1 and leaving true or unbarred the literals that are a binary 0. Then each input of a given product term is applied to the control gate of a P channel device, which devices are connected in series with one end tied to a source of potential and the other end of the series circuit connected to an output terminal. Each product term is arranged in parallel with other P channel device series circuits to form one half of a complete logic matrix. Similarly, for the other half of the matrix, a sum-of-products expression giving the binary 0 outputs of a truth table having a binary 1 for an input is found. Each input of a given product term is applied to the control gate of an N channel device, which devices are connected in series with one end tied to a potential reference point, such as ground, and the other end of the series circuit is connected to the output terminal. Each product term is arranged in parallel with other N channel device series circuits.

REFERENCES:
patent: 3252011 (1966-05-01), Zuk
patent: 3643232 (1972-02-01), Kilby
patent: 3945000 (1976-03-01), Suzuki et al.
patent: 4069426 (1978-01-01), Hirasawa
patent: 4482810 (1984-11-01), Cooke

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