Multi-register interrupt controller with multiple interrupt dete

Details Multi-register interrupt controller with multiple interrupt dete Multi-register interrupt controller with multiple interrupt dete

1991-07-19

1995-04-25

Bowler, Alyssa H.

395800, 395375, G06F 900

Patent

active

054107083

ABSTRACT:
An interrupt controller has an interrupt controller, an interrupt control register having registers each including first and second flip-flops, a channel selector, and a read/write circuit. The interrupt controller receives interrupt requests from external devices and transmits these interrupt requests to external processing devices. The interrupt control register includes registers for recording data to control operation of the interrupt controller and the state of a plurality of interrupt requests. The channel selector assigns one register from the registers. The first flip-flop indicates the generation of an initial interrupt request. The second flip-flop indicates the generation of following interrupt requests when the first flip-flop has already been set to indicate the generation of the initial interrupt request. The read/write means, connected to the second flip-flop, writes data into the second flip-flop based on control signals from the external devices and outputs the data of the second flip-flop to the external devices.

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IBM Technical Disclosure Bulletin, vol. 32, No. 8A, Jan. 1990, pp. 323-325 "Mechanism For Sharing Edge-Sensitive Interrupts".

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