Boots – shoes – and leggings
Patent
1985-01-02
1986-05-27
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 1516
Patent
active
045919712
ABSTRACT:
A digital computer has an addressable store 1, which may comprise segments 1a, 1b, etc. and a plurality of independent digital processing units 3a, 3b, etc. all communicating with the store 1 through a communication facility 2.
Addresses in store 1 containing packets of digital data which require processing are held in a group of identifier stores 4a, 4b, etc. to which group the processing units all have access. Where processing results in the generation of fresh packets of data addresses for such data in store 1 are held in a second group of identifier stores 5a, 5b to which the processing units also have access. Controllers 6a, 6b, etc. and 7a, 7b, etc. ensure even transfer of identifier address among the stores of a group and act as interfaces between the identifier stores and the processing units.
REFERENCES:
patent: 3648252 (1972-03-01), Thron et al.
patent: 4130885 (1978-12-01), Dennis
"A Multi-Processor Reduction Machine for User-Defined Reduction Languages", by Philip C. Treleaven and Geoffrey F. Mole, Computing Laboratory, The University of Newcastle upon Tye, England, May 1980, Conference Proceedings, The 7th Annual Symposium on Computer Architecture.
"Computer Cells--A Network Architecture for Data Flow Computing", by David L. Nelson, Robert L. Gordon, Prime Computer, Inc., Framingham, Mass., 1978.
"A Computer Simulation Facility for Packet Communication Architecture", by Clement K. C. Leung, David P. Misuanas, Andrij Neczwid and Jack B. Dennis, Institute of Electrical and Electronics Engineers, Proceedings of the 3rd Annual Symposium on Computer Architecture; Jan. 1976, vol. 3.
"A Peripheral Array Computer and its Applications", by H. Schomberg, Philips GmbH Forschungslaboratorium Hamburg, 2000 Hamburg 54, FRG 1977.
Darlington John
Reeve Michael J.
National Research Development Corporation
Zache Raulfe B.
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