In-register data manipulation for unaligned byte write using dat

Details In-register data manipulation for unaligned byte write using dat In-register data manipulation for unaligned byte write using dat

1994-08-10

1995-04-25

Bowler, Alyssa H.

Boots, shoes, and leggings

395400, 395425, 36423223, 3642526, 3642551, 364DIG1, G06F 1204, G06F 1576

Patent

active

054106826

ABSTRACT:
A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.

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