Logic simulator

Details Logic simulator Logic simulator

1993-03-23

1995-04-25

Voeltz, Emanuel T.

Excavating

371 251, 324731, G01R 3128

Patent

active

054105498

ABSTRACT:
There is disclosed a logic simulator including a logic circuit verifying portion (3) that records in a floating information storage portion (4) generation and end times of a floating state with respect to a signal provided from a node specified by a through current verification node data (D3) as a function of a circuit connection data (D2) during the execution of a logic simulation and compares each floating node information (d13) in a floating node information group (D13) accumulated in the floating information storage portion (4) with a through current generation critical; period (D12) after the completion of the logic simulation to perform a through current generation verification, thereby achieving an automatic verification of the presence of an undesired current such as a through current generated in a logic circuit with high accuracy.

REFERENCES:
patent: 4601032 (1986-07-01), Robinson
patent: 4771428 (1988-09-01), Acuff et al.
patent: 4852093 (1989-07-01), Koeppe
patent: 4937765 (1990-06-01), Shupe et al.
patent: 5291495 (1994-03-01), Udell, Jr.

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