Method for distributing a clock signal within a semiconductor in

Details Method for distributing a clock signal within a semiconductor in Method for distributing a clock signal within a semiconductor in

1992-06-10

1995-04-25

Teska, Kevin J.

Boots, shoes, and leggings

364489, G06F 1546

Patent

active

054104912

ABSTRACT:
A clock-signal distributing method used in a wiring-pattern network such that a clock signal is supplied from root driver cells via repeating buffer cells to terminal cells. The method comprises the steps of: grouping the terminal cells into clusters containing at least one of the terminal cells, forming a binary-tree-shaped wiring pattern path where the root driver cells are root nodes and the clusters are leaf nodes, inserting the repeating buffer cells into the wiring pattern path at which delay time required for clock signal transmission in the binary-tree-shaped path is minimized, calculating first delay amounts in a signal path defined from a branch node at a low level of the binary-tree-shaped path to the leaf nodes, setting physical positions of the branch nodes such that a difference among the calculated first delay amounts is minimized, separating the overlapped terminal cells from each other on the binary-tree-shaped path by updating previous information about a circuit connection when the repeating buffer cells are inserted and by correcting arrangement information about terminal cell positions adjacent to the buffer cells, determining a final wiring-pattern path within each of the clusters based upon the corrected arrangement information, calculating second delay amounts in the clusters based on the finally determined wiring-pattern path, determining respective branch node positions based on the second delay amounts, and determining a final wiring-pattern path among the branch nodes.

REFERENCES:
patent: 4811237 (1989-03-01), Putatunda et al.
patent: 4815003 (1989-03-01), Putatunda et al.
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5262959 (1993-11-01), Chkoreff
Jackson et al., "Clock-Routing for High-Performance ICs", ACM/IEEE Design Automation Conference, Jun. 24, 1990, pp. 573-579.
Boon et al., "High Performance Clock Distribution for CMOS ASICs", IEEE Custom Integrated Circuits Conference, 1989, pp. 15.4.1-15.4.5.
H. B. Bakoglu et al., "A Symmetric Clock-Distribution Tree and Optimized High-Speed Interconnections for Reduced Clock Skew in ULSI and WSI Circuits", IEEE 1986, pp. 118-122.

Affiliated with

Also associated with

Rating

Method for distributing a clock signal within a semiconductor in does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for distributing a clock signal within a semiconductor in, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for distributing a clock signal within a semiconductor in will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1572390