Reset circuit for a programmable logic device

Details Reset circuit for a programmable logic device Reset circuit for a programmable logic device

1996-06-26

1997-11-18

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

056895160

ABSTRACT:
A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.

REFERENCES:
patent: 5598421 (1997-01-01), Tran et al.
patent: 5610927 (1997-03-01), Segars
patent: 5617431 (1997-04-01), Topuri et al.
patent: 5623502 (1997-04-01), Wang
"The Programmable Logic Data Book", 1994, pp. 3-1 through 3-90, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.

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