Semiconductor memory device

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371 21, 371 24, G11C 2900, G06F 1100

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046673300

ABSTRACT:
A semiconductor memory chip which has not only a memory array together with address decoding means, but also a self diagnosis means which functions to indicate a defective cell of said memory array has been found. Said self diagnosis means is mounted on the same chip as that of the memory array, and has means for storing information to be stored in the memory array, and means for comparing content of said storing means with output information which is read out of the address at which the information is stored. When the two data do not coincide with each other, an error signal indicating a defective cell in the memory array at the selected address is output.

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J. J. LeBlanc, LOCST: A Built-In Self-Test Technique, IEEE Design and Test, Nov. 1984, pp. 45-52.
E. F. Hahn et al., VLSI Testing by On-Chip Error Detection, IBM Technical Disclosure Bulletin, vol. 25, No. 2, Jul. 1982, p. 709.
P. P. Fasang, Circuit Module Implements Practical Self-Testing, Electronics, May 19, 1982, pp. 164-167.
T. W. Williams, High-Speed Low-Volume Data Array Self-Test, IBM Technical Disclosure Bulletin.

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