Method for optimizing thermal budgets in fabricating semiconduct

Details Method for optimizing thermal budgets in fabricating semiconduct Method for optimizing thermal budgets in fabricating semiconduct

1993-08-06

1995-04-25

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437982, 148DIG133, H01L 2126, H01L 21268

Patent

active

054098580

ABSTRACT:
A method for fabricating semiconductors is provided in which a conformal layer is formed superjacent at least two conductive layers. The conformal layer has a thickness of at least 50 .ANG.. A barrier layer is then formed superjacent the conformal layer to prevent subsequent layers from diffusing into active regions. The barrier layer is preferably Si.sub.3 N.sub.4. A glass layer is then formed superjacent the barrier layer. The glass layer has a thickness of at least 1 k.ANG.. The glass layer is heated to a temperature of at least 800.degree. C. for at least 15 minutes while introducing H.sub.2 and O.sub.2 at a high temperature to cause vaporization, thereby causing the glass layer to reflow. Next, the glass layer is exposed to a gas and radiant energy for 5 to 60 seconds, thereby making said glass layer planar. The radiant energy generates a temperature within the range of 700.degree. C. to 1250.degree. C. Further, the gas is at least one of N.sub.2, NH.sub.3, O.sub.2, N.sub.2 O, Ar, Ar-H.sub.2, H.sub.2, GeH.sub.4, and a fluorine based gas.

REFERENCES:
patent: 4630343 (1986-12-01), Pierce
Wolf et al., vol. I, Silicon Processing for the VLSI Era, Lattice Press, 1986.
Wolf et al., vol. II, Silicon Processing for the VLSI Era, Lattice Press, 1990.
"Improvement of Dielectric Integrity of TiSi.sub.x -Polycide-gate System by Using Rapidly Nitrided Oxides" by T. Hori, N. Yoshii & H. Iwasaki8, pp. 2571-2574, 1988 Fabricated Silicon Nitride Films.
"Reduced Thermal Budget Borophosphosilicate glass (BP56) Fusion and Implant Activation Using Rapid Thermal Annealing and Steam Reflow" , R. Thakas et al. Materials Research Society Mar. 1993.

Affiliated with

Also associated with

Rating

Method for optimizing thermal budgets in fabricating semiconduct does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for optimizing thermal budgets in fabricating semiconduct, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for optimizing thermal budgets in fabricating semiconduct will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1567317