Integrated circuit fabrication

Details Integrated circuit fabrication Integrated circuit fabrication

1995-11-30

1997-11-18

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437 44, 437203, 257288, H01L 218232

Patent

active

056887043

ABSTRACT:
A method of integrated circuit fabrication is disclosed. Layers of silicon nitride and silicide dioxide are formed upon a silicon substrate. These layers are etched to create a channel having the width of the intended gate. The silicon dioxide is then wet etched. Next, polysilicon is deposited within the channel. The silicon dioxide and the silicon nitride layers are then removed. A T-shaped polysilicon gate facilitates the formation of rectangular-shaped silicon nitride spacers. Subsequent salicidation is performed.

REFERENCES:
patent: 5171698 (1992-12-01), Shimoda
patent: 5231038 (1993-07-01), Yamaguchi et al.
patent: 5288660 (1994-02-01), Hua et al.
patent: 5432126 (1995-07-01), Oikawa
IBM Tech. Discl. Bulletin, 28(7)(1985)2767 "Self-Aligned Dummy Gate Sidewall-Spaced MESFET", Dec. 1985.

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