Method of fabricating a stacked capacitor memory cell in a semic

Details Method of fabricating a stacked capacitor memory cell in a semic Method of fabricating a stacked capacitor memory cell in a semic

1995-02-02

1996-01-30

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 60, 437919, 437977, H01L 2170, H01L 2700

Patent

active

054880084

ABSTRACT:
A method of manufacturing a capacitor, in a semiconductor memory device having memory cells, each including a transistor and a capacitor includes steps of depositing an insulating film on a semiconductor substrate and forming a polycrystalline silicon film serving as a lower electrode of the capacitor on the insulating film. An oxide film having an uneven surface is deposited on the polycrystalline silicon film by exposing the polycrystalline silicon film to an oxidizing atmosphere including N-type impurities. The polycrystalline silicon film and the oxide film are anisotropically etched until the oxide film is substantially completely removed. The uneven surface of the oxide layer produces an uneven etch rate of the polycrystalline silicon film and a magnification of the uneven surface of the oxide film in the polycrystalline silicon film.

REFERENCES:
patent: 5134086 (1992-07-01), Ahn
patent: 5164881 (1992-11-01), Ahn
Wolf et al. Silicon Processing for the VLSI ERA vol. 1, Process Technology, pp. 181-182, 264-266, 556-558.
Silicon Processing for the VLSI ERA, vol. 1 Process Technology, Wolf, pp. 551-557, Lattice press.
Rugged Surface Poly-Si Electrode And Low Temperature Deposited Si.sub.3 N.sub.4 For 64MBIT And Beyond STC Dram Cell IEDM (1990) pp. 659-662.

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