Static information storage and retrieval – Addressing
Patent
1996-09-12
1997-07-22
Fears, Terrell W.
Static information storage and retrieval
Addressing
365222, 36523006, G11C 1300
Patent
active
056509758
ABSTRACT:
In a memory plane of a semiconductor memory device, transmission gate circuits for transferring data between local I/O line pair and global I/O line pair, and equalizing circuits for equalizing the local I/O line pair are arranged alternately on both sides of a shunt region. All the global I/O line pairs extend entirely over the memory plane. One and the other global I/O lines are arranged in symmetry, with a line for transmitting bit line precharge voltage, cell plate voltage or local input/output line equalizing signal being the center.
REFERENCES:
patent: 5040144 (1991-08-01), Pelley et al.
patent: 5097440 (1992-03-01), Konishi et al.
patent: 5184321 (1993-02-01), Konishi et al.
patent: 5321646 (1994-06-01), Tomishima et al.
patent: 5325336 (1994-06-01), Tomishima et al.
"A 64Mb DRAM with Meshed Power Line and Distributed Sense-Amplifier Driver", T. Yamada et al., 1991 IEEE International Solid-State Circuits Conference, pp. 108-109.
"A 40ns 64Mb DRAM with Current-Sensing Data-Bus Amplifier", M. Taguchi et al., 1991 IEEE International Solid-State Circuits Conference, pp. 112-113.
Asakura Mikio
Hamade Kei
Hidaka Hideto
Yasuda Ken'ichi
Fears Terrell W.
Mitsubishi Denki & Kabushiki Kaisha
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