Memory address control device with extender bus

Details Memory address control device with extender bus Memory address control device with extender bus

Filed on

1977-01-03

Date issued

1979-06-26

Examiner

Springborn, Harvey E.

Patent Class

Boots, shoes, and leggings

Other Related Categories

G06F 1300

Type

Patent

Status

active

Patent number

041595203

Description

ABSTRACT:
A control memory address generation device, for use as a single device or in a slice environment, performs logical and/or data path selection functions with respect to control information from an arithmetic and logic unit or a control word field, or both, to generate the next control memory address. A flexible register organization and extender bus logic allows subroutining control, instruction or subroutine repetition, masking, branching (conditional or unconditional), and other address-related operations.

REFERENCES:
patent: 3665402 (1972-05-01), Greenspan et al.
patent: 3736567 (1973-05-01), Lotan et al.
patent: 3766527 (1973-10-01), Briley
patent: 3972024 (1976-07-01), Shroeder et al.
IBM 7080 Data Processing System (Reference Manual A22-6560-1), 1961, pp. 12-19, 25-28, 31-36, 62-64, cover page & preface.
"A Primer on Bit-Slice Processors", --Nemec et al--Electronic Design 3, Feb. 1977, --pp. 52-60.

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