Low voltage erase of a flash EEPROM system having a common erase

Details Low voltage erase of a flash EEPROM system having a common erase Low voltage erase of a flash EEPROM system having a common erase

1996-07-08

1997-10-14

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518531, 36518533, G11C 1604

Patent

active

056778724

ABSTRACT:
A flash EEPROM is organized on an integrated circuit with individual erase gates being shared by two adjacent blocks (sectors) of memory cells. This reduces the number of erase gates and the complexity of the driving erase circuitry. Each of the two adjacent blocks are individually addressable for erasing. The control gates of the cells within the block that is not to be erased are held at a voltage close to that of the common erase gate, thus preventing their storage states from being disturbed. At the same time, the control gates of the block to be erased are held at a voltage that differs sufficiently from that of the erase gate to cause the erasure. In order to minimize the magnitude of the erase voltages, voltages applied to the common erase gate and the control gates of the block to be erased are substantially equal and of opposite polarities.

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Kazerounian et al., "A 5 Volt High Density Poly-Poly Erase Flash EPROM Cell" IDEM, pp. 436-439 (1988).

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