Memory with isolatable expandable bit lines

Details Memory with isolatable expandable bit lines Memory with isolatable expandable bit lines

1995-06-30

1997-10-14

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365 53, 365218, G11C 1300

Patent

active

056778678

ABSTRACT:
The invention enables random read and write operations into cells in an array that contains connections from the memory cells that include at least one field effect transistor (FET transistor) to embedded bit line segments which are selectively isolatable and selectively expandable to achieve compactness of number of cell per unit area.
In a given segment of the array a first select transistor is connected between a given embedded bit line segment and a first access bit line which functions as a path from a first reference voltage to the drain of a first FET memory transistor set when the first select transistor is turned off, and wherein the first access bit line functions as a path from the source of a second FET memory transistor set to a second reference voltage when the first select transistor is turned on. A second select transistor connected between the embedded bit line segment and a second bit line which functions as a path from said first reference voltage to the drain of a second Memory FET set when the second select transistor is turned off, and wherein said second bit line functions as a path from the source of the first Memory FET set to a second reference voltage when said first select transistor is turned on.
The invention also reduces the diffusion isolation spacing between bit-lines by using shield transistors.

REFERENCES:
patent: 4903105 (1990-02-01), Matsumoto
patent: 5111428 (1992-05-01), Liang et al.
patent: 5117389 (1992-05-01), Yiu
patent: 5151375 (1992-09-01), Kazerounian et al.
patent: 5204835 (1993-04-01), Eithan
B. J. Lin "The Attenuated Phase-Shifting Mask, Solid State Technology, " pp. 43-47, Jan. 1992.
Y.C. See et al., "An Alignment-Tolerant Contact Process using Landing Pads", Motorola Inc. Tech. Dev., vol. 12, pp. 17-18 Apr. 1991.

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