Central processing unit and an arithmetic operation processing u

Details Central processing unit and an arithmetic operation processing u Central processing unit and an arithmetic operation processing u

1995-02-02

1997-10-14

Malzahn, David H.

Boots, shoes, and leggings

395562, G06F 9302

Patent

active

056778597

ABSTRACT:
An arithmetic operation processing unit provided with an external program memory storing a high speed instruction group for executing a specific routine of arithmetic operations which require high speed execution is shown. The arithmetic operation processing unit comprises a start address register for holding a starting address of the specific routine of arithmetic operations and an end address register for holding an end address of the specific routine of arithmetic operations, an FIFO type RAM for storing microcodes obtained by decoding the high speed instruction group. The high speed instruction group stored in the program memory is sequentially read out by a first instruction execution control means from the start address to the end address and decoded into corresponding microcodes when a high speed instruction group decoding instruction is executed. The microcodes thus obtained are then stored in the FIFO type RAM. The microcodes thus stored in the FIFO type RAM are executed one for each clock when a high speed instruction group execution instruction is executed.

REFERENCES:
patent: 5038312 (1991-08-01), Kojima
patent: 5311458 (1994-05-01), Haines
patent: 5430852 (1995-07-01), Watanabe et al.
patent: 5473557 (1995-12-01), Harrison et al.
patent: 5473764 (1995-12-01), Chi

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