Cascadable peripheral data interface including a shift register,

Static information storage and retrieval – Magnetic bubbles – Guide structure

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395493, 36518912, 365236, 3652385, 365219, 364DIG1, 3642451, 3642474, 364DIG2, 3649333, G06F 1204, G06F 1200, G11C 1928, G11C 700

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054540976

ABSTRACT:
A cascadable peripheral (10) has at least two registers (51, 52, 53) of different sizes. Input data is shifted serially through a shift register (40) synchronously with a clock signal. A serial output of the shift register (40) is provided to a data output terminal (18) of the peripheral (10) for cascading. A counter (20) increments a state in response to the clock signal. A decode portion (30, 31, 32, 33, 35) activates one of a group of load signals, corresponding to one of the registers (51, 52, 53), in response to a state of the counter (20), when an enable signal becomes inactive. The active load signal causes the corresponding register to load a value presented from a parallel data output of the shift register (40). The counter (20) is reset in response to either the enable signal becoming inactive or the counter (20) reaching a maximum count corresponding to a size of the shift register (40).

REFERENCES:
patent: 4084154 (1978-04-01), Panigrahi
patent: 5146577 (1992-09-01), Babin
patent: 5262907 (1993-11-01), Duffy et al.

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