Virtual to physical address translation scheme with granularity

Details Virtual to physical address translation scheme with granularity Virtual to physical address translation scheme with granularity

1993-08-24

1995-09-26

Rudolph, Rebecca L.

Boots, shoes, and leggings

395445, 395496, 39542102, 3642563, 3642551, G06F 1210

Patent

active

054540917

ABSTRACT:
A high-performance central processing unit (CPU) of the reduced instruction set (RISC) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry.

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