Method of making asymmetrical N-channel and P-channel devices

Details Method of making asymmetrical N-channel and P-channel devices Method of making asymmetrical N-channel and P-channel devices

1996-09-03

1997-10-14

Niebling, John

Fishing, trapping, and vermin destroying

437 34, 437 44, 437 58, 257274, 257336, 257338, 257369, H01L 2170

Patent

active

056772246

ABSTRACT:
An asymmetrical N-channel IGFET and an asymmetrical P-channel IGFET are disclosed. One or both IGFETs include a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region. Preferably, the heavily doped source region and lightly doped drain region provide channel junctions. Forming a first asymmetrical IGFET includes forming a gate with first and second opposing sidewalls over a first active region, applying a first ion implantation to implant lightly doped source and drain regions into the first active region, applying a second ion implantation to convert substantially all of the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming first and second spacers adjacent to the first and second sidewalls, respectively, and applying a third ion implantation to convert a portion of the heavily doped source region outside the first spacer into an ultra-heavily doped source region without doping a portion of the heavily doped source region beneath the first spacer, and to convert a portion of the lightly doped drain region outside the second spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the second spacer. A second asymmetrical IGFET is formed in a related manner. Advantageously, one or both IGFETs have low source-drain series resistance and reduce hot carrier effects.

REFERENCES:
patent: 5286664 (1994-02-01), Horiuchi
patent: 5424229 (1995-06-01), Oyamatsu
U.S. Patent Application, Serial No. 08/682,238, filed Jul. 17, 1996, entitled "Method For Fabrication Of A Non-Symmetrical Transistor", by Mark I. Gardner, Derick J. Wristers and H. Jim Fulford, Jr.
U.S. Patent Application, Serial No. 08/682,493, filed Jul. 17, 1996, entitled "Method For Fabrication Of A Non-Symmetrical Transistor", by Mark I. Gardner, Michael P. Duane and Derick J. Wristers.

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