Method for selectively filling contacts or vias or various depth

Details Method for selectively filling contacts or vias or various depth Method for selectively filling contacts or vias or various depth

1989-12-29

1991-01-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437245, 437246, 437228, H01L 2148

Patent

active

049870998

ABSTRACT:
A method of making planarized metallization on a semiconductor substrate employing selective deposition.

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"Plasma Etching Methods for the Formation of Planarized Tungsten Plugs Used in Multilevel VLSI Metallizations", Saia et al., Solid-State Science and Tech., vol. 135, No. 4, pp. 936-940 (Apr. 1988).
"High Conductivity Diffusions and Gate Regions Using Self-Aligned Silicide Technology", Osburn et al., VLSI Science and Tech. (1982).

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