Method for manufacturing a DRAM with reduced cell area

Details Method for manufacturing a DRAM with reduced cell area Method for manufacturing a DRAM with reduced cell area

1996-10-07

1997-10-14

Tsai, Jey

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 218242

Patent

active

056772238

ABSTRACT:
The present invention relates to a method of forming a capacitor on a semiconductor substrate. A first dielectric layer is formed on a semiconductor substrate. A contact hole is created in the first dielectric layer. A polysilicon layer is formed on the first dielectric layer and in the contact hole. Subsequently, a second dielectric layer is formed on the first polysilicon layer. A photoresist is patterned on the second dielectric layer. A oxygen plasma etching is used to narrow the photoresist. A etching is performed by using the narrowed photoresist as a mash to etch the second dielectric layer. The narrowed photoresist is then stripped to formed a insulator pillar. A second polysilicon layer is deposited on the first polysilicon layer and on the pillar. An etching process is used to etch the second polysilicon layer to form sidewall spacers on the sidewall of the pillar. The pillar is then removed by HF vapor. A dielectric film is coated along the surface of the first polysilicon layer and the sidewall spacers. A third polysilicon layer is then formed on the dielectric film.

REFERENCES:
patent: 5021357 (1991-06-01), Taguchi et al.
patent: 5302540 (1994-04-01), Ko et al.
patent: 5374580 (1994-12-01), Baglee et al.
patent: 5399518 (1995-03-01), Sim et al.
patent: 5403766 (1995-04-01), Miyake
patent: 5585303 (1996-12-01), Hong et al.

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