Method for forming a DRAM capacitor

Details Method for forming a DRAM capacitor Method for forming a DRAM capacitor

1996-10-11

1997-10-14

Niebling, John

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170

Patent

active

056772220

ABSTRACT:
An improved method for forming a dynamic random access memory (DRAM) capacitor with increased capacitance is disclosed. The method includes forming an oxide layer on a semiconductor substrate with a metal-oxide-semiconductor field effect transistor (MOSFET) conventionally formed therein and thereon. A planarized silicon nitride layer is then formed on the oxide layer. Then alternating layers of dielectric layers having different etch rates are formed on the silicon nitride layer. Standard photolithographic methods are used to etch a trench through the dielectric layers and the silicon nitride layer to expose the source region of the MOSFET. The trench is then isotropically etched, forming rounded cavities in portions of the dielectric layers having the faster etch rate. The rounded cavities extend horizontally into the sidewalls of the trench. A doped polysilicon layer is then formed on the top of the dielectric layers so as to fill the trench and the rounded cavities. The polysilicon layer is then patterned and etched to removed the polysilicon layer around the trench. The dielectric layers are then removed, thereby forming the bottom electrode of a DRAM cell capacitor.

REFERENCES:
patent: 5137842 (1992-08-01), Chan et al.
patent: 5478769 (1995-12-01), Lim
patent: 5506163 (1996-04-01), Moriya
patent: 5545582 (1996-08-01), Roh

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