Method of manufacture DRAM capacitor with reduced layout area

Details Method of manufacture DRAM capacitor with reduced layout area Method of manufacture DRAM capacitor with reduced layout area

1996-06-19

1997-10-14

Niebling, John

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170

Patent

active

056772211

ABSTRACT:
A method of manufacturing a capacitor for use in a DRAM. The method includes forming an isolation layer over a substrate, forming a nitride layer over the isolation layer, forming a hole in the isolation and nitride layers, forming a polysilicon plug in the hole, growing an oxide plug from an upper portion of the polysilicon plug, removing the nitride layer, forming a polysilicon spacer around the oxide plug, and removing the silicon dioxide plug. Additional steps include depositing a dielectric layer onto the polysilicon sidewall and plug, and depositing a third polysilicon layer onto the dielectric layer.

REFERENCES:
patent: 5137842 (1992-08-01), Chan et al.
patent: 5399518 (1995-03-01), Sim et al.
patent: 5478769 (1995-12-01), Lim
patent: 5510289 (1996-04-01), Choi

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