Process for manufacturing stacked semiconductor devices

Details Process for manufacturing stacked semiconductor devices Process for manufacturing stacked semiconductor devices

1988-06-09

1991-01-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 49, 437 56, 437156, 437158, 437915, 437162, H01L 21225

Patent

active

049870920

ABSTRACT:
An improved method of manufacturing semiconductor devices having a stacked structure is disclosed. A p-channel semiconductor substrate is prepared, and on the major surface of the substrate, n-channel source and drain regions and a gate electrode are formed to provide a n-channel transistor. Sidewalls are formed of P type single-crystal silicon on the opposite size of the gate electrode of n-channel transistor with an insulating layer interposed between the sidewalls and the gate electrode. A single-crystal layer covers the source, drain and gate electrode of the n-channel transistor and the sidewall structures. A P type impurity present in the sidewalls is diffused into the single-crystal layer.

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IEDM 84: "A Fully Self-Aligned Stacked CMOS 64K SRAM", by R. Sundaresan et al., 34.9 1984, pp. 871-873.
Colinge et al., "A High Intensity CMOS Inverter with Stacked Transistors", IEEE Electron Device Letters, vol. EDL-2, No. 10, Oct. 1981, pp. 250-251.

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