Lateral bidirectional dual notch shielded FET

Details Lateral bidirectional dual notch shielded FET Lateral bidirectional dual notch shielded FET

1982-06-21

1986-02-18

Clawson, Jr., Joseph E.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307584, 357 234, 357 238, 357 2314, 357 39, 357 41, 357 43, 357 86, H03K 17687

Patent

active

045715130

ABSTRACT:
Lateral FET Structure is disclosed for bidirectional power switching, including AC application. A pair of notches, each with a gate electrode, extend downwardly from a top major surface to separate left and right source regions and left and right channel regions, and direct the drift region current path between the channels around the bottoms of the notches. In the OFF state, each gate electrode shields its respective notch edge drift region portion from the electric field gradient from the other gate electrode, to prevent depletion along the notches and unwanted inducement of conduction channels, thus affording higher OFF state voltage blocking capability. High density, high voltage plural FET structure is disclosed.

REFERENCES:
patent: 3798514 (1974-03-01), Hayashi et al.
patent: 4199774 (1980-04-01), Plummer
J. Tihanyi, "Funct. Integ. of Power MOS and Bipolar Devices," Proc. 1980 IEEE IEDM, Dec. 1980, pp. 75-78.
"A Parametric Study of Power MOSFET'", C. Hu, IEEE Electron Device Confeence; Paper CH 1461-3/79, 0000-0385.
IEEE Transactions Electron Devices, vol. ED-25; #10; Oct. 1978.
"UMOS Transistors on (110) Silicon", Ammar & Rogers, Transactions IEEE; ED-27; May 1980; pp. 907-914.
"Optimum Doping Profile for Minimum Ohmic Resistance and High Breakdown Voltage", C. Hu; IEEE Transactions Electron Devices; vol. ED-26; 1970; pp. 243-244.
P. Ou-Yang, "Double Ion Implanted V-MOS Tech," IEEE J. of S.-S. CKTS., vol. SC-12, #1, Feb. 1977, pp. 3-10.

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