Output circuit having decreased interference between output term

Details Output circuit having decreased interference between output term Output circuit having decreased interference between output term

1983-08-24

1986-02-18

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307473, 307577, 307304, 307296R, H03K 19094

Patent

active

045715092

ABSTRACT:
An output circuit for a semiconductor integrated circuit is improved by reverse biasing the gates of non-selected output field effect transistors (MOSTs). A control MOST, when actuated by a chip-select signal, connects the gate of its associated output MOST with a negative voltage so that the non-selected output MOSTs are completely cut off. The invention avoids the problem which arises with the use of very short channel output MOSTs such that the channel cannot be completely cut off if a zero bias is applied to the gate.

REFERENCES:
patent: 4256978 (1981-03-01), Pinckaers
patent: 4296340 (1981-10-01), Horan
patent: 4345172 (1982-08-01), Kobayashi et al.
patent: 4378506 (1983-03-01), Taira
patent: 4395645 (1983-07-01), Pernyeszi
Homan, "FET Depletion Load Push-Pull Logical Circuit", IBM Tech. Disc. Bull., vol. 18, No. 3, Aug. 1975, pp. 910-911.

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