Method and apparatus of reducing latch-up susceptibility in CMOS

Details Method and apparatus of reducing latch-up susceptibility in CMOS Method and apparatus of reducing latch-up susceptibility in CMOS

1983-11-16

1986-02-18

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307296R, 307579, H03K 17693

Patent

active

045715050

ABSTRACT:
Method and apparatus for controlling latch-up in a CMOS circuit senses a power supply transition, clamps the substrate to ground in response to sensing a power supply transition, and releases the clamp after the power supply transition. A charge pump pumps the substrate illustratively to -3 volts. The charge pump, clamping transistor and related elements are on the same CMOS substrate where latch-up is to be controlled. The substrate to ground capacitance of the substrate is increased to prevent localized substrate voltage disturbances which may induce latch-up.

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