Method of making a silicon controlled rectifier device for elect

Details Method of making a silicon controlled rectifier device for elect Method of making a silicon controlled rectifier device for elect

1994-03-25

1995-09-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 27, 437 28, 437 38, 437 39, 257107, 257124, H01L 4900

Patent

active

054533848

ABSTRACT:
A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58). A gate insulator region (233) is formed over adjacent regions of the semiconductor layer (222) and of the lightly doped region (224) to be interposed between the first (226) and third (230) heavily doped regions, such that the gate insulator region (233) is formed over a junction (236) between the semiconductor layer (222) and the lightly doped region (224). A polysilicon gate layer (237) is formed over the gate insulator region (233) and is electrically coupled to the first node (62).

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Chatterjee, et al.; "A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads", IEEE Electron Device Letters, pp. 21-22, vol. 12, No. 1, Jan. 1991.

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