Interframe encoding system having a buffer simulator

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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375 33, H04N 713

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active

046333126

ABSTRACT:
According to the present invention, an encoding system has an interframe encoder for interframe encoding of video signals to supply predictive encoded signals, and a scan converter for converting the predictive encoded signals into predictive encoded signals of a predetermined block structure. A code converter converts effective picture elements in the block-structured predictive encoded signals into variable length codes and ineffective picture elements therein into run length codes. A buffer memory not only stores the code-converted codes but also calculates their occupancy quantity. The present encoding system is further provided with a buffer simulator for calculating, on the basis of the predictive encoded signals and the code-converted signals, the quantity of information stored in the scan converter, an adder for adding simulated information and the buffer occupancy quantity, and a control circuit for controlling generation of interframe encoding information on the basis of the added signals.

REFERENCES:
patent: 4051530 (1977-09-01), Kuroda
patent: 4517596 (1985-05-01), Suzuki
patent: 4534055 (1985-08-01), Iinuma
IEEE Transactions on Communications, vol. COM-29, No. 12, pp. 1868-1876, Dec. 1981.

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