Dual stack power JFET with buried field shaping depletion region

Details Dual stack power JFET with buried field shaping depletion region Dual stack power JFET with buried field shaping depletion region

1984-06-08

1986-12-30

Clawson, Jr., Joseph E.

357 20, 357 52, 357 55, 357 59, 357 41, 357 68, 357 86, H01L 2980

Patent

active

046332812

ABSTRACT:
A power JFET (2) has a common drift region (4) between a pair of spaced first and second stacks (6, 8) of alternating conductivity type layers (10-14 and 15-19) forming a plurality of channels (11, 13, 16 and 18). The JFET has an ON state conducting bidirectional current horizontally through the common drift region and the channels. The channels are stacked vertically, and the JFET has an OFF state blocking current flow through the channels due to vertical depletion pinch-off. Field shaping and high blocking voltage capability are provided. Particular main terminal and gate structure is disclosed.

REFERENCES:
patent: 2820154 (1958-01-01), Kurshan
patent: 2954486 (1960-09-01), Doucette et al.
patent: 2989713 (1961-06-01), Warner
patent: 3035186 (1962-05-01), Doucette
patent: 3354362 (1967-11-01), Zuleeg
patent: 3878552 (1975-04-01), Rodgers
patent: 4338618 (1982-07-01), Nishizawa
"Simultaneous Modulation of Electron and Hole Conductivity in a New Periodic GaAs Doping Multilayer Structure", K. Ploog et al., Applied Physics Letters, vol. 38, No. 11, Jun. 1981, pp. 870-873, New York.

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