Single ended MOS to ECL output buffer

Details Single ended MOS to ECL output buffer Single ended MOS to ECL output buffer

1990-03-01

1991-07-30

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307264, 307443, H03K 19092, H03K 19094

Patent

active

050362240

ABSTRACT:
An output buffer circuit which converts CMOS logic levels to ECL logic levels. ECL high and ECL low level voltage signals are generated by a reference network. A switch responds to the status of a pair of complementary CMOS inputs to selectively connect one of the ECL voltage signals to an ECL load.

REFERENCES:
patent: 4533842 (1985-08-01), Yang et al.
patent: 4704549 (1987-11-01), Sanwo et al.
patent: 4782251 (1988-11-01), Tsugaru et al.
patent: 4890019 (1989-12-01), Hoyte et al.
patent: 4947061 (1990-08-01), Metz et al.

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