Reduced input capacitance analog storage array

Details Reduced input capacitance analog storage array Reduced input capacitance analog storage array

1993-05-24

1995-04-11

Heyman, John S.

Static information storage and retrieval

Analog storage systems

365102, 327 94, 327427, H03K 1700

Patent

active

054065070

ABSTRACT:
Reduction of input capacitance in an analog storage array is achieved by reducing the parasitic capacitance presented to an analog signal line. Each column of the analog storage array is coupled to the analog signal line by a separate coupling switch. The switches are activated so that no more than two columns are coupled to the analog signal line at any time, with the next column to be accessed being coupled to the analog signal line prior to access to that column, and the last column being decoupled from the analog signal line after the last cell in the column has been accessed. Further the analog signal line may provide two input ports so that alternate columns of the array are coupled to one port, and the other alternate columns are coupled to the other port so that two adjacent columns are coupled to separate ones of the two ports.

REFERENCES:
patent: 3986174 (1976-10-01), Wisseman et al.
patent: 4922452 (1990-05-01), Larsen et al.
patent: 5210777 (1993-05-01), Warabu et al.

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